3D Networks-on-Chip mapping targeting minimum signal TSVs
نویسندگان
چکیده
منابع مشابه
3D Networks-on-Chip mapping targeting minimum signal TSVs
The sharply increased complexity of multi-core systems has motivated the architecture of Networks-on-Chip (NoC) to evolve from 2D to 3D. With the objective of optimizing 3D NoC system for specific applications, a new mapping scheme with the goal of reducing signal TSVs and peak temperature is proposed in this paper. The interlayer communication is optimized, which facilitates reduction of signa...
متن کاملDesigning TSVs for 3D Integrated Circuits
It's not surprisingly when entering this site to get the book. One of the popular books now is the designing tsvs for 3d integrated circuits. You may be confused because you can't find the book in the book store around your city. Commonly, the popular book will be sold quickly. And when you have found the store to buy the book, it will be so hurt when you run out of it. This is why, searching f...
متن کاملCost-aware Topology Customization of Mesh-based Networks-on-Chip
Nowadays, the growing demand for supporting multiple applications causes to use multiple IPs onto the chip. In fact, finding truly scalable communication architecture will be a critical concern. To this end, the Networks-on-Chip (NoC) paradigm has emerged as a promising solution to on-chip communication challenges within the silicon-based electronics. Many of today’s NoC architectures are based...
متن کاملApplication Mapping onto Network-on-Chip using Bypass Channel
Increasing the number of cores integrated on a chip and the problems of system on chips caused to emerge networks on chips. NoCs have features such as scalability and high performance. NoCs architecture provides communication infrastructure and in this way, the blocks were produced that their communication with each other made NoC. Due to increasing number of cores, the placement of the cores i...
متن کاملElixir: A new bandwidth-constrained mapping for Networks-on-chip
Nowadays, with technology shrinking and the huge demand for supporting multiple applications has led designers to use multiple IP cores within a single chip. Therefore, the designers have proposed Networks-on-chip to overcome the problems of future complex systems. Mapping IPs directly affects NoC design parameters such as latency and power consumption. In this paper we present a power and perf...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: IEICE Electronics Express
سال: 2013
ISSN: 1349-2543
DOI: 10.1587/elex.10.20130518